1. Field of the Invention
This invention relates to data caches, and particularly to a method and apparatus for implementing a combined data/coherency cache.
2. Description of Background
In a large shared-memory multiprocessor, providing a system-level cache of the recently accessed contents of memory, along with an efficient means to handle system-wide cache coherency, can be accomplished with a single system cache directory array by requiring the contents of the respective processor-level caches to be a subset of the system cache. Unfortunately, when the combined size of the processor caches is sufficiently large, this subset rule can become impractical because of the resulting size of the system cache required to work effectively becomes too big. While one possible solution to this is to maintain two directories (one for the system cache, one for all the processor cache contents), this complicates the design significantly. Using two separate directories to accomplish the same task requires more logic, both to synchronize the contents of the two directories (either to keep them distinct, or to manage them if allowed to overlap), as well as to carry out any system memory access (which requires looking up both directories and taking the appropriate action in each).
What is needed, therefore, is a single system cache directory that is large enough to contain all the processor cache directory entries, but with only sufficient system cache to back the most recent fraction of data accessed by the processors.